Embodiments of the present disclosure relate to a nonvolatile memory device and a method of operating the same and, more particularly, to a single-layer gate electrically erasable programmable read-only memory (EEPROM) cell, a cell array including the same, and a method of operating the cell array.
An EEPROM device is a nonvolatile memory device that retains stored data even when not powered. In an EEPROM device, data is electrically stored in memory cells, and the stored data is electrically erased. Various memory cell structures of the EEPROM device have been proposed to improve performance. A typical memory cell of an EEPROM device employs a stacked gate structure in which a floating gate, an inter-gate dielectric layer, and a control gate are sequentially stacked on a semiconductor substrate.
As electronic systems become smaller with the development of fabrication techniques of semiconductor devices, system-on-chip (SOC) products have been utilized as important devices of high performance digital systems. An SOC product may include a plurality of semiconductor devices executing various functions in a single chip. The SOC product may include at least one logic device and at least one memory device, which are integrated in a single chip. Thus, fabrication technologies of an embedded EEPROM device may be required to embed an EEPROM device in an SOC product.
In order to embed an EEPROM device in an SOC product, the fabrication technologies of the embedded EEPROM device have to be compatible with the fabrication technology of the logic device included in the SOC product. In general, a logic device employs transistors having a single gate structure, while the EEPROM device employs cell transistors having a stacked gate structure (e.g., a double gate structure). Thus, an SOC product including an EEPROM device and a logic device may require a complicated fabrication technology. Accordingly, a single-layer gate EEPROM device employing a single-layer gate cell structure is an attractive candidate for use in an embedded EEPROM device. Complementary metal-oxide-semiconductor (CMOS) circuits of the logic device may be readily implemented using the fabrication technology of the single-layer gate EEPROM device. As a result, the fabrication technology of single-layer gate EEPROM device may be widely used in fabrication of an SOC product including an embedded EEPROM device.
In general, an embedded EEPROM device requires a fast access time. Thus, the embedded EEPROM device may be designed to have a NOR-type cell array configuration rather than a NAND-type cell array configuration. In such a case, there may be some limitations in designing peripheral circuits which are capable of preventing read errors from occurring due to over-erased unit cells in a read mode.
Read errors, which occur due to the over erasure phenomenon, may be resolved by modifying methods of operating the unit cells or methods of arranging the unit cells in the embedded EEPROM device. Further, a high performance embedded EEPROM device may be fabricated by preventing non-selected unit cells from being affected or disturbed by voltages applied to a selected unit cell during a program mode or a read mode. Moreover, in order to fabricate a high performance embedded EEPROM device, the embedded EEPROM device may be designed to operate at a low program voltage and a low erasure voltage. This is for scaling down MOS transistors of the embedded EEPROM device to increase a degree of integration of the embedded EEPROM device.